Introduction to Vias

This Gold Phoenix PCB Knowledge Center article introduces PCB vias — their types, parasitic effects, and design recommendations for high-speed applications. In brief, each hole on a PCB can be called a via. From a functional perspective, vias can be divided into two categories: one is used for electrical connection between layers, and the other is used as a device for fixing or positioning.

From a manufacturing process perspective, vias are generally divided into three categories: blind via, buried via, and through via.

• A blind via is located on the top or bottom surface of the printed circuit board and has a depth that is used for the connection of the surface trace and the inner trace below. The depth of the hole usually does not exceed a certain ratio.

• A buried via is a connecting hole in the inner layer of a printed circuit board that does not extend to the surface of the circuit board. Blind vias connect an outer layer to one or more inner layers, while buried vias connect inner layers to each other without reaching either surface. Both types are formed during the lamination process and may be overlapped in the process of hole formation.

• A through via passes through the entire circuit board and can be used for internal interconnection or as a mounting hole for components. Since through vias are easier to implement and lower in cost, most printed circuit boards use them instead of the other two types.

The vias discussed below are through vias unless otherwise specified. From a design perspective, a via is made up of two main parts: the drill hole (the central hole) and the pad area around the hole. The size of these two sections determines the size of the via. In high-speed and high-density PCB design, designers always prefer through holes to be as small as possible so the board can have more wiring space. In addition, a smaller hole results in lower parasitic capacitance, which is more suitable for high-speed circuits. However, decreasing the hole size also brings cost increases, and the hole size cannot be reduced without limit.

There are two manufacturing limitations:

1. Drilling: A smaller hole requires longer drilling time and is easier to deviate from the center position.

2. Electroplating: When the depth of the hole exceeds 6 times the hole diameter, the hole wall cannot guarantee uniform copper plating. For example, the thickness of a standard 6-layer PCB board (through-hole depth) is about 50 mil, so the smallest drill hole diameter provided by the PCB manufacturer can only reach 8 mil.

Parasitic Capacitance of Vias

Through-hole vias have parasitic capacitance. If D2 is the diameter of the isolation hole in the ground layer, D1 is the pad diameter, T is the PCB plate thickness, and ε is the substrate dielectric constant, the parasitic capacitance of the via is approximately:

C = 1.41 × ε × T × D1 / (D2 − D1)

The parasitic capacitance of the via causes the main effect on the circuit by prolonging the signal rise time and reducing the speed of the circuit.

Example: For a PCB with 50 mil plate thickness, using a 10 mil inner diameter (drill hole), 20 mil pad diameter, and 32 mil isolation hole diameter in the ground layer:

• C = 1.41 × 4.4 × 0.05 × 0.02 / (0.032 − 0.02) = 0.517 pF

• The rise time variation caused by this capacitance: T10–90 = 2.2 × C × (Z0/2) = 2.2 × 0.517 × (55/2) = 31.28 ps

From these values, it can be seen that the delay caused by the parasitic capacitance of a single via is not very obvious. However, if a trace repeatedly switches between layers through vias, the designer should consider this effect carefully.

Parasitic Inductance of Vias

Vias also have parasitic inductance. In the design of high-speed digital circuits, the harm caused by parasitic inductance is often greater than that of parasitic capacitance. Parasitic inductance will weaken the contribution of bypass capacitors and reduce the filtering effectiveness of the entire power supply system.

The following formula can be used to calculate an approximation of the parasitic inductance of a via:

L = 5.08h [ln(4h/d) + 1]

Where:

• L is the inductance of the through hole

• h is the length (depth) of the through hole

• d is the diameter of the center bore

It can be seen from the formula that the diameter of the through hole has little influence on the inductance, and the length of the through hole is the most influential factor.

Example: Using the same values as above to calculate the inductance of the via:

• L = 5.08 × 0.05 × [ln(4 × 0.05 / 0.01) + 1] = 1.015 nH

• If the signal rise time is 1 ns, the equivalent impedance is: XL = π × L / T10–90 = 3.19 × L / 1 ns = 3.19 ohms

This impedance at high frequency cannot be ignored. In particular, when bypass capacitors are connected through two vias to the power and ground planes, the parasitic inductance of the vias will increase.

High-Speed PCB Design Recommendations

Based on the analysis of parasitic characteristics of through-hole vias, it can be seen that in high-speed PCB design, seemingly simple holes can often bring negative effects to the circuit design. In order to reduce the adverse effects caused by the parasitic effects of vias, the following measures can be taken:

1. Select a reasonable through-hole size. Consider both cost and signal quality. For example, in 6–10 layer memory module PCB design, using 10/20 mil (drill/pad) through holes is a good choice. For some high-density, small-size boards, 8/18 mil through holes can also be used. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, a larger size may be considered to minimize impedance.

2. Use thinner PCB plates. The two formulas discussed above show that reducing the plate thickness can lower both parasitic parameters of vias.

3. Minimize layer changes. Avoid unnecessary vias on signal traces. In other words, do not change layers unless it is necessary.

4. Place power and ground pins close to through holes. The power and ground leads should be as thick as possible to reduce impedance.

5. Place ground vias near signal vias. Ground vias should be placed near the vias of the signal transfer layer to provide the closest return path for the signal. A number of redundant ground vias can even be placed on the PCB board.

Of course, flexibility is needed in design. The standard via model discussed above includes a pad for each layer, but sometimes pads on some layers can be reduced or even removed. Especially when the via density is very large, vias may lead to a broken circuit or partition groove formed on a copper layer. To solve this problem, in addition to moving the position of the hole, the size of the hole pad on the copper layer can also be decreased.