How to Create a Printed Circuit Board (PCB)

Executive Summary

This Gold Phoenix PCB Knowledge Center article walks through the full PCB design and fabrication workflow — from prototyping and schematic capture to physical layout, Gerber file creation, board fabrication, and the lessons engineers learn along the way. It is written for product engineers, hardware designers, and buyers who need a practical map of the manufacturing side of PCB production, not just the CAD tool side.

The process splits into two halves. The design half — schematic capture, component selection, and physical layout — happens in your CAD software. The fabrication half — lamination, drilling, plating, solder mask, and electrical test — happens inside a PCB factory. The handoff between the two is the Gerber (and drill) files, and most production problems trace back to a mismatch between what the designer assumed and what the fabricator can actually hold to.

Each chapter below expands on one step in the design-to-fabrication process and links out to a dedicated reference article. Engineers new to PCB manufacturing should read through the chapters in order, because each step builds on the previous one. The original Section block at the bottom of this page lets you jump directly to any individual tutorial chapter. Engineers who already know the basics can skip ahead to the chapters most relevant to their current production issue.

1. Overview

A printed circuit board is a sandwich of copper foil and insulating dielectric layers, patterned and etched so that electrical signals connect components in a defined way. Before any layout begins, the team should agree on the board’s functional requirements: number of signals, impedance targets, voltage rails, layer count, and the mechanical enclosure it must fit into. These inputs drive every downstream decision, from trace width to stack-up thickness. A board designed for a high-speed digital application has very different impedance and routing requirements than a low-voltage analog sensor board.

The typical production flow is: prototype → schematic capture → component selection → physical layout → design rule check → Gerber output → fabrication → assembly → test. Each step has its own common failure modes, and skipping a review at any stage multiplies cost later in the cycle. The chapters below expand on each step, with links to deeper reference articles for engineers who need the technical detail. This guide assumes the reader has a basic familiarity with CAD tools like Altium, KiCad, or Eagle, and focuses on what happens on the factory floor after the design files are exported.

Related: Chapter 1: Overview of PCB Production

2. Prototyping

Prototyping is the phase where the design moves from a block diagram to a bill of materials. Early prototypes are usually 2-layer or 4-layer boards built quickly, to validate the schematic and mechanical fit before committing to a high-layer-count production run. The goal is not to hit cost targets yet; it is to catch functional and layout mistakes cheaply. A prototype board that costs twice the per-unit price of production is still far cheaper than a respin discovered after the production run.

During prototyping, engineers should order extra panels, keep a second source for critical components, and document every change. The decisions made here — connector footprint, component placement orientation, and keep-out zones — lock in hard once the production Gerber is sent. A 2-hour layout fix during prototyping can become a 2-day respin after fabrication, and the cost of delayed time-to-market usually dwarfs the cost of the extra prototype run. It is also good practice to prototype the critical analog or high-speed sections first, since those are the circuits most sensitive to layout parasitics and stack-up choices.

Related: Chapter 2: Prototyping

3. Schematic Capture

Schematic capture is where the circuit becomes a logical netlist. Every component, power rail, and signal is drawn with its reference designator, value, and pinout. Good schematic practice means grouping functional blocks, labeling nets clearly, and keeping decoupling capacitors physically adjacent to the IC pins they serve. A clean schematic halves the time needed to debug the first board bring-up, because the layout engineer can trace signal paths without guessing at the designer’s intent.

Common schematic mistakes include floating inputs, missing pull-up resistors, and mislabeled power domains. The layout engineer should not have to guess which net is 3.3V and which is 5V. A netlist error that survives into the layout stage is far more expensive to fix than one caught on the schematic, because it now has to be untangled from routed traces and placed components. A 10-minute schematic review before the netlist export prevents hours of rework later. It is also worth checking that every component in the BOM matches the schematic footprint, and that any designators with multiple parts have been properly annotated.

Related: Chapter 3: Schematic Capture

4. Physical Layout

Physical layout translates the netlist into copper traces on a layer stack. This is where component placement, trace routing, plane splitting, and via placement happen. High-speed signals need controlled impedance references and return paths that are continuous; analog and digital sections should be separated to avoid noise coupling. The layout pass also sets solder mask openings, silkscreen references, and fiducial marks for automated assembly.

Layout engineers should follow DFM rules early: minimum trace width and spacing, annular ring size, via diameter, and solder mask expansion. These constraints are not arbitrary — they reflect the manufacturer’s drill, etch, and plating capabilities. Ignoring them leads to open circuits, insufficient copper adhesion, or solder mask slivers. A design that passes the CAD tool’s default DRC but ignores the fabricator’s stack-up capabilities is still likely to yield scrap. For high-speed designs, the stack-up itself must be specified before routing begins, because the dielectric thickness and copper weight determine the trace width needed to hit 50-ohm or 100-ohm impedance targets.

Related: Chapter 4: Physical Layout

5. Physical Creation of PCB

The fabrication house receives the Gerber and drill files and turns them into physical boards. The process starts with core lamination, where copper layers are pressed onto prepreg at high temperature and pressure. Then drilling removes copper where vias and holes need to go, followed by electroless copper plating that coats the hole walls. Outer layers are etched to the final trace pattern, solder mask is applied and exposed, and a surface finish — typically ENIG, HASL, or OSP — protects the copper from oxidation before assembly.

After bare-board fabrication, the boards move to assembly, where components are placed and soldered. The PCB assembly process covers solder paste deposition, SMT placement, reflow profiling, and through-hole insertion. For high-pin-count packages, a BGA package requires extra attention to solder ball coplanarity and reflow temperature profiles. Surface finish choice matters here too: a poorly controlled ENIG process can cause ENIG black pad, where the nickel surface corrodes and solder joints fail even though the board passed bare-board test. Once assembled, many products add a protective conformal coating type chosen for the operating environment — acrylic, urethane, silicone, or parylene.

Related: Chapter 5: Physical Creation of PCB

6. Lessons Learned and Recommendations

Every fabrication run produces lessons. The most expensive mistakes are usually not exotic failures — they are the same repeated issues: insufficient annular ring, unconnected thermal reliefs, missing solder mask between fine-pitch pins, and unlabeled test points. Keeping a post-mortem checklist across projects prevents the same respin from recurring. Teams that document their first five design mistakes rarely repeat them on the sixth project.

Before sending the final Gerber, run a full DRC, cross-check the drill file against the layer stack, and verify the panelization and break-away rail layout. A 30-minute file review catches issues that would otherwise cost days of delay and thousands of dollars in reruns. It is also worth confirming with the fabricator that the impedance stack-up and surface finish are available in the production schedule, rather than assuming they are standard stock. For designs with controlled impedance requirements, request an impedance test coupon on the panel so the fabrication house can verify the actual dielectric constant and copper plating on the production lot.

Related: Chapter 6: Lessons Learned and Recommendations

7. Appendix

The appendix collects reference material: common stack-up configurations, standard via sizes for different layer counts, surface finish comparison tables, and DFM checklist templates. Engineers can use these as a starting point for their own design review rather than rebuilding the reference table from scratch each project. It also includes a glossary of fabrication terms — lamination, prepreg, core, CTE, Dk, Df, annular ring, and breakout — so that design and manufacturing teams share the same vocabulary when discussing a drawing.

For engineers new to PCB fabrication, the appendix also lists the typical lead times and minimum order quantities for different board types, so that scheduling decisions can be made with realistic manufacturing constraints rather than optimistic assumptions.

Related: Chapter 7: Appendix

schematic capture to physical layout, Gerber file creation, board fabrication and testing.

Section

1. Overview

2. Prototyping

3. Schematic Capture

4. Physical Layout

5. Physical Creation of PCB

6. Lessons Learned and Recommendations

7. Appendix